A Novel Evolvable Hardware Framework for the Evolution of High Performance Digital Circuits

This paper presents a novel evolvable hardware framework for the automated design of digital circuits for high performance applications. The technique evolves circuits corresponding to each specific output, under restricted functionality and timing constraints. The individual circuits are then processed to generate the completed circuit. Applications have focused on the design of multi-output arithmetic circuits, such as a 3-bit multiplier. Circuit evolution is performed within a Virtual Chip environment, a fusion of C code, VHDL and CAD tool for synthesis. As a result of the tools used within the Virtual Chip, constraints such as timing are taken into account during evolution. Both primitive gates and functional macro blocks are available to the framework providing a flexible means for generating complex digital circuits. A 3-bit multiplier, evolved by our framework, is compared to an equivalent circuit generated through standard design techniques, and is found to be of comparable performance. An additional comparison is made with a multiplier evolved using a conventional evolvable hardware framework which does not use the phased approach to circuit evolution.